TM DSG SiNT MOSFET with a inner gate and outer gate are shown with

I On /I Off ratio comparison of this work with literature

Effect of 3 nm gate length scaling in junctionless double

TM DSG SiNT MOSFET with a inner gate and outer gate are shown with

ION/IOFF ratio comparison of this work with reports in literature

I On /I Off ratio comparison of this work with literature

Real and imaginary energy dispersion for the Δ minimum of the

Device structure for 10 nm DG In0.53Ga0.47As NMOSFET with SiO2 +

CGG vs VGS curve of Si for SiO2 + HfO2 as gate oxide with metal

Anil VOHRA, Professor (Full), M.Sc., Ph.D

ID versus VDS curves of TM DSG SiNT MOSFET with

ID versus VDS curves of TM DSG SiNT MOSFET with

IG vs VGS curves with Ta and W as metal gates for In0.53Ga0.47As